1. Field of the Invention
The present invention relates to the impedance control of an output driver of a semiconductor integrated circuit, particularly to a semiconductor integrated circuit including an impedance matching circuit for autonomously performing output impedance adjustment and an impedance control method thereof.
2. Description of Related Art
With higher data transfer rate in data transfer between semiconductor devices and lower power consumption of the whole system that mounts a semiconductor integrated circuit thereon, demands and requirements for devices have been increased that can enhance impedance matching between an output driver and a transmission line as well as reduce the power consumption.
In the data transfer between semiconductor devices, when the output impedance of the output driver of the semiconductor integrated circuit is not matched to the impedance of the transmission line, reflection of a data signal outputted from the output driver occurs. In performing impedance matching, since a replica resistor likened to the impedance of the transmission line is used, the impedance of the transmission line is easy to change due to external factors such as the temperature. The output impedance of the semiconductor integrated circuit is easy to change due to an operating voltage in the circuit and temperature variation. Therefore, an impedance matching circuit for detecting change of the impedance and autonomously correcting the impedance has been provided.
Although the impedance matching circuit that can autonomously adjust the impedance has been used in the semiconductor integrated circuits such as the SRAM (Static Random Access Memory) that operate at high speed, they have not been used so much in the semiconductor integrated circuits such as the DRAM (Dynamic Random Access Memory) or the pseudo SRAM that require an operation with low power consumption. Accordingly, in most cases, reduction of power consumption of the impedance matching circuit itself has not been demanded. However, with higher data transfer rate in recent years, in order to prevent false transmission caused by reflection of the output data signal, impedance matching is being essential also in the DRAM and the pseudo SRAM. Furthermore, lower power consumption is being demanded in the semiconductor integrated circuits such as the SRAM that operate at high speed.
FIG. 1 is a diagram showing a configuration of a main part of a DRAM equipped with an autonomous impedance adjustment circuit according to a conventional technique.
Referring to FIG. 1, a DRAM according to the conventional technique includes a semiconductor integrated circuit 200 that outputs data outputted from a memory cell array to a processor. The semiconductor integrated circuit 200 is configured to autonomously adjust the output impedance and includes an output driver 50 that can change its current drive capability (current drivability) and an impedance matching circuit 60 having replica drivers P80, N80 that can change their current drive capability. Outputs of the replica drivers P80, N80 are coupled to corresponding replica resistors R71, R72, respectively. The impedance matching circuit 60 adjusts the current drive capability of the output driver 50 and the replica drivers P80, N80 based on output voltages of the replica drivers P80, N80 and a reference voltage. The semiconductor integrated circuit 200 is implemented in a single semiconductor package.
The impedance matching circuit 60 includes the replica drivers P80, N80, comparators P60, N60 and up/down (U/D) counters P70, N70. The replica driver P80 has the same configuration as that of a pull-up side circuit including a pull-up side transistor group of the output driver 50 and has the same output impedance as the pull-up side circuit. An output of the replica driver P80 is coupled to the replica resistor R71 having the same impedance as the characteristic impedance of a transmission line (data bus 51) coupled to the output driver 50. The comparator P60 compares an output voltage level of the replica driver P80 with a predetermined voltage level (VDDQ/2 in FIG. 1). The U/D counter P70 is a counter counting up or down according to a comparison result of the comparator P60. The current drive capability of the pull-up side circuit of the replica driver P80 and the output driver 50 is configured to change depending on the count value of the U/D counter P70. With the above-mentioned configuration, a value held in the U/D counter P70 converges, thereby achieving the impedance matching between the output of the replica driver P80 and the replica resistor R71.
In the impedance matching circuit 60, a structure for adjusting the output impedance of a pull-down side circuit of the output driver 50 is provided with components symmetrical to the components in the above-mentioned pull-up side circuit. The replica driver N80 has the same configuration as the pull-down side circuit including a pull-down side transistor group of the output driver 50 and the same output impedance as the pull-down side circuit. An output of the replica driver N80 is coupled to the replica resistor R72 having the same impedance as the characteristic impedance of the transmission line (data bus 51) coupled to the output driver 50. The comparator N60 compares the output voltage level of the replica driver N80 with a predetermined voltage level (VDDQ/2 in FIG. 1). The U/D counter N70 is a counter counting up or down according to a comparison result of the comparator N80. The current drive capability of the pull-down side circuit of the replica driver N80 and the output driver 50 is configured to change depending on the count value of the U/D counter N70. With the above-mentioned configuration, a value held in the U/D counter N70 converges, thereby achieving impedance matching between the output of the replica driver N80 and the replica resistor R72.
As described above, the current drive capability of the output driver 50 and the replica drivers P80, N80 is changed so as to match the impedances of the replica drivers P80, N80 to the impedances of the replica resistors N71, R72, respectively, in turn, match (automatically adjust) the output impedance of the output driver 50 to the impedance of the transmission line (data bus 51).
As an example of the autonomous output impedance adjustment circuit of conventional techniques, a semiconductor integrated circuit is described in Japanese Patent Application Publication JP 2008-118382 (referred to as Patent Literature 1). In the semiconductor integrated circuit described in Patent Literature 1, by adjusting the output impedance in synchronization with a clock signal generated in a semiconductor device such as a self-refresh timer, even when supply of an external clock is stopped, the operation of adjusting the output impedance can be stably continued.